1. Field of the Invention
The present invention relates to a phase comparator, a DLL (Delay Locked Loop) circuit and a semiconductor integrated circuit, and more particularly, to a phase comparator used in a DLL circuit for controlling delay time by using a delay stage and a shift register.
2. Description of the Related Art
Recently, semiconductor integrated circuits have been designed to realize high speed operation and low power consumption. For example, with regard to clock signals, it has become necessary to control a semiconductor integrated circuit by supplying phase synchronized clock signals to a predetermined circuit therein.
Concretely, memory devices developed in recent years have attained operation speeds that exceed 100 MHz, and thus, there has been used a method of making the phases of an external input clock signal and an internal clock signal coincide with each other by utilizing DLL techniques to thereby exclude the influence of a delay resulting from an internal clock wire or line so as to remove a delay or fluctuation of an access time.
In accordance with such DLL techniques, a memory device is adapted so that a dummy circuit is provided therein so as to estimate the propagation delay caused by an internal output clock signal line load.
Concretely, for example, a synchronous DRAM (SDRAM) is adapted so that signals phase-synchronized with external clock signals by using a DLL circuit are supplied to a plurality of output buffer circuits. There is a demand for reduction in the time taken until a DLL circuit locks up at power-up and at power-on/reset.
The related art phase comparator (DLL circuit) and problems associated therewith will be described in detail later with reference to drawings.